Gate-all-around nanowire field effect transistors (FETs) in a vertical configuration can be considered strong candidates to extend today’s CMOS technology to its ultimate scaling limits. With an excellent performance/area ratio, they seem particularly attractive for making highly dense static random access memory (SRAM) cells. Moreover, when used to building those SRAM cells, vertical nanowire FETs may play a key role in hybrid scaling – an emerging scaling approach that integrates multiple transistor architectures in one system-on-chip.
In this article, Nadine Collaert (distinguished member of technical staff at imec), Anabela Veloso (principal member of technical staff at imec) and Trong Huynh-Bao (R&D engineer at imec) highlight the opportunities brought by vertical nanowire FETs. They also discuss the possible device integration routes and talk about the ‘super-scaling’ of SRAM cells.
Moving towards hybrid scaling
Traditional device scaling has been one of the cornerstones of the semiconductor industry ever since Gordon Moore presented ‘Moore’s Law’ back in 1965. More recently, however, another trend has started to emerge on the technology roadmap: hybrid scaling – also referred to as hybridized scaling, heterogeneous scaling or heterogeneous integration.
"The fundamental difference with traditional device scaling is that hybrid scaling features no preferred device architecture that makes up a system."
Instead, multiple device technologies are applied to create different subsystems of a system-on-chip, depending on their function in the system. For example, magnetoresistive random access memory (MRAM) could be used for embedded cache memory, aggressively scaled FinFETs for the highest performance CPU cores, and spin logic devices for ultra-low-power functions. In the context of future hybrid scaling, the vertical nanowire field effect transistor (FET) has the potential to become an important player as well. As recently shown at imec, it is a promising technology for enabling highly dense static random access memory (SRAM) cells.
The vertical nanowire FET
Gate-all-around (GAA) nanowire/nanosheet FETs are, to a certain extent, a natural evolution of today’s FinFET technology. In these devices, the gate is fully wrapped around the thin conduction channel (the nanowire) of the transistor, allowing superior short channel electrostatic (SCE) control, as required for more advanced technology nodes. The technology also promises further density scaling, which becomes increasingly problematic because of challenges in gate pitch scaling.
Nanowire FETs can be implemented in a lateral or a vertical configuration. That said, devices in a lateral configuration still use conventional 2D layouts, and hence their scaling into advanced nodes will eventually hit physical limits, similarly to FinFETs. For example, the space available for gate and contact placement will become too small. Moreover, in the back-end-of-line, too many metal lines in increasingly narrow spaces will give rise to interconnect routing congestion.
And that’s where the vertical GAA nanowire FETs come into play. With these devices, we move from a 2D to a 3D layout configuration, wherein the gate length is defined vertically. Such a disruptive innovation requires early process-design co-optimization, but it also leads to new opportunities.