Imec’s Indiana center
Imec and Purdue University combine their expertise to tackle major challenges around semiconductor scaling and sustainability.
Chip technology has a stunning history, but its greatest challenges and most exciting times are still ahead of us.
New applications such as artificial intelligence require increased performance. However, traditional scaling – putting more transistors on the same surface – is becoming increasingly difficult, especially when using silicon.
Growing concerns about sustainability also need to be addressed. Chips must become radically more power-efficient to avoid exploding energy use, which would have a devastating effect on climate goals. Furthermore, the use of harmful chemicals involved in semiconductor manufacturing processes must be reduced.
As the chip lab of the world, imec plays a crucial role in the industry's success by fostering collaboration across the ecosystem. Through enhanced, deeper, and locally integrated partnerships, we aim to ensure that tomorrow's technology meets society's needs. Our local collaboration with Purdue University in Indiana, which has remained a powerhouse of semiconductor research for almost a century, aligns perfectly with this approach.
Focus research topics
At this moment, researchers from imec and Purdue University are working closely together on ‘4S’: sustainable & synergistic semiconductor systems. This encompasses these topics:
1. 2D materials for exploratory advanced logic
When it comes to the future of transistor scaling, the increased occurrence of short-channel effects in silicon presents a major roadblock. The introduction of 2D materials could provide a solution, but major developments are needed – particularly towards industrial adoption.
More info on the value of introducing 2D-material-based devices to the logic scaling roadmap
By combining their talent, know-how, and expertise, imec and Purdue University aim to make significant contributions to this crucial research topic.
2. Advanced packaging
Another means of continuing Moore’s law as traditional scaling runs out of steam is advanced packaging.
Techniques such as 3D stacking and chiplet integration allow for more efficient use of space and power, enhancing overall system performance.
3. Co-design (STCO)
System-technology co-optimization (STCO) is pivotal for advancing semiconductor performance by aligning system-level design with technology capabilities. STCO involves the co-design of hardware and software, ensuring that the entire system operates in unison, overcoming the limitations of traditional scaling.
4. Sustainability
Over the last few years, the semiconductor industry has become increasingly concerned about its environmental impact. This applies to carbon emissions related to the chip manufacturing process, but also to the use of chemicals such as PFAS.
Reducing or even eliminating PFAS from semiconductor fabrication is a complex task, as it’s embedded in a variety of processing steps. Researchers at imec’s Indiana center and Purdue University specifically address the detection of PFAS and its separation from lithography waste streams, in close tandem with their colleagues in imec’s Sustainable Semiconductor Technologies and Systems (SSTS) program.
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