Imec achieves new milestones in single patterning High NA EUV lithography for both damascene and direct metal etch metallization processes

• Imec demonstrates line structures at 20nm pitch with 13nm tip-to-tip dimensions relevant for damascene metallization, as well as 20nm and 18nm pitch ruthenium lines in a direct metal etch (DME) process – both obtained with single-print High NA EUV lithography. For the 20nm pitch DME line structures, an electrical test yield of 100% was obtained.
• These results mark a milestone in the single patterning capabilities of High NA EUV lithography for future metallization schemes, in support of advanced logic use cases.
• “The joint ASML-imec High NA EUV Lab plays a strategically critical role in accelerating the adoption of High NA EUV lithography, which is a key enabling technology for the EU’s NanoIC pilot line. These achievements were made possible by dedicated experts collaborating within imec’s strong partner ecosystem, driving EUV lithography R&D and guiding the industry into the angstrom era.”

LEUVEN (Belgium), September 22, 2025— This week, at the 2025 SPIE Photomask Technology + EUV Lithography Conference (Monterey (CA)), imec, a world-leading R&D center in advanced semiconductor technologies, presents two breakthrough achievements in single print High NA EUV lithography: (1) line structures at 20nm pitch with 13nm tip-to-tip critical dimension (CD) relevant for damascene metallization, and (2) electrical test results of Ru lines at 20nm pitch obtained with a direct metal etch (DME) process. These results, enabled in part by the EU’s NanoIC pilot line, not only mark a major milestone in advancing the single print capabilities of High NA EUV patterning. They also underscore the pivotal role of the imec-ASML partnership in enabling the broader ecosystem that drives the High NA EUV transition to high volume manufacturing, unlocking the sub-2nm logic technology roadmap. 

After demonstrating 20nm pitch metallized line structures at the 2025 SPIE Advanced Lithography and Patterning in February 2025, imec now achieves 20nm pitch line structures with 13nm tip-to-tip (T2T) critical dimension (CD) with a single-exposure High NA EUV lithography step. For the 13nm T2T structures, a local CD uniformity (LCDU) as low as 3nm was measured, marking an industry milestone. The results were obtained with a metal oxide resist (MOR), which was co-optimized with underlayer, illumination pupil shape and mask selection. 

Steven Scheer, Senior Vice President Compute System Scaling at imec: “Achieving these logic designs with single print High NA EUV lithography reduces processing steps compared to multi-patterning, lowering fabrication costs and environmental impact, and improving yield. These results support damascene metallization, the industry standard for interconnect fabrication. T2T structures are an essential part of the interconnect layers, as they allow for interrupting the one-dimensional metal tracks. To meet the logic roadmap at 20nm metal pitch, the T2T distance is expected to scale to 13nm and below. while maintaining functional interconnects. Developments are ongoing to further scale T2T dimensions, with promising results for 11nm T2T, and to transfer the structures into an underlying hard mask – enabling true (dual-)damascene interconnects.”

To enable metallization below 20nm, industry will likely move to alternative metallization schemes.   As a second achievement, imec demonstrates the compatibility of direct metal etch (DME) of ruthenium (Ru) with single exposure High NA EUV lithography. We achieved Ru lines at 20nm and 18nm pitch, including 15nm T2T structures and functional interconnects with low resistance. For the 20nm pitch metallized line structures, an electrical test yield of 100% was obtained.

Steven Scheer: “After the opening of the joint ASML-imec High NA EUV lab in Veldhoven, the Netherlands, imec and its ecosystem of partners made great strides in advancing High NA EUV lithography and launching the industry into the angstrom era – backed by three years of ecosystem preparation. The presented results mark a new milestone, underscoring imec’s leadership in litho R&D. They also play a critical role in realizing the European Chips Act’s ambitions for enabling sub-2nm logic technology nodes. In close collaboration with the imec-ASML High NA EUV ecosystem, which includes leading chip manufacturers, equipment, material and resist suppliers, mask companies, and metrology experts, we continue to jointly optimize High NA EUV lithography and patterning in support of the logic and memory roadmaps.”

The results, enabled in part by the EU’s NanoIC pilot line, will be presented in the following paper at the SPIE Photomask Technology + EUV Lithography Conference:

Paper 13686-4 - Advances of dry resist towards next-generation lines-spaces patterning in high NA EUV lithography