Three flavors of iSiPP
Imec's iSiPP platform is SOI-based and comes in three distinct flavors:
- iSiPP200: 200mm (8”) full platform (see table below)
- iSiPP50G: 200mm (8”) simplified platform/flow (see table below)
- iSiPP300: 300mm (12”) full platform
Prototyping services
|
iSiPP50G |
iSiPP200 |
||
|
Access model |
MPW |
Shared run |
Dedicated run |
|
Functionality |
Basic (23 modules) |
Full (30 modules) |
Full (30 modules) |
|
Silicon delivery |
Dies from up to 3 wafers |
Dies from up to 3 wafers |
Full wafers (minimum 15) |
|
Run timing |
Fixed |
Semi-flexible |
Flexible, upon request |
|
Minimum area |
5mm x 5mm |
Quarter reticle (10mm x 9mm) |
Full reticle (21.5mm x 18.5mm) |
|
Metrology/test |
Standard test |
Standard test |
Standard test |
|
Customization |
Limited (upon availability) |
Options available (Semi Flexible) |
Options available (Fully Flexible) |
|
Cost sharing |
Mask and processing |
Mask and some processing |
None |
Key technology parameters
- Starting substrate: Silicon-on-insulator with 220nm Si / 2000nm BOX
- 3-level Si & 1-level poly-Si patterning with 193nm lithography
- 6-level silicon doping & 2-level Ge doping
- Ge-on-Si RPCVD epitaxy
- 2-level Cu interconnects + Al bondpad
- Deep-Si etch for edge coupling
Available devices
- Traveling–wave Mach-Zehnder p-n modulator
- Ge(Si) electro-absorption modulator
- Micro-ring p-n modulator
- Waveguide-based Ge-on-Si detectors
- Fiber coupling:
- Vertical “raised” grating
- C-band edge coupler
- Passive waveguide-based devices such as filters
- Integrated heaters
How can we help you?
Some examples of what we have done
At imec bright people build a bright future.
You could be one of these builders. Whether you are an engineer or an operator, a consultant or PhD student, we need a versatile group of people to help us create positive change.
Join the forward thinkersJob opportunities
Group Leader Thin Film Deposition Process Engineering
As an inspirational Group Leader for Thin Films Deposition (TFE), with a strong technical background in the area of PVD, CVD, ALD, Epitaxy and Furnace techniques, you are responsible for the day-to-day support to the Fab in these techniques.
R&D Etch Specialist
As R&D Engineer Etch Process, you will provide etch process solutions and an understanding of the interactions between etch and the overall integration scheme.
ASIC Test Engineer
Test Engineer for ndustrialization of new products
FOWLP Integration Engineer
Join the 3D team at imec’s R&D headquarters located in the heart of Europe and help in revolutionizing next-generation integrated 3D systems as Fan Out Wafer Level Packaging engineer.
More job opportunities