2TnC Ferroelectric Memories

The semiconductor industry is steadily advancing toward three-dimensional (3D) integration to meet the growing demands for higher memory density and reduced cost per bit. While traditional charge-based memory technologies, such as DRAM and Flash, face physical and scalability limitations in 3D architectures, emerging memory technologies are being explored to overcome these constraints. Ferroelectric memories (FeRAMs), benefiting from low-power operation, high speed, and non-volatility, are particularly promising for vertical scaling. Their compatibility with CMOS processes and potential for ultra-dense memory arrays make them strong candidates for next-generation 3D memory solutions.

Ferroelectric memories utilize the reversible polarization of ferroelectric materials, typically hafnium oxide-based, to store information in a non-volatile manner. Various device architectures have been proposed, including capacitor-based FeRAMs, ferroelectric tunnel junctions (FTJs), and ferroelectric field-effect transistors (FeFETs). Among these, the nC-string architecture—where multiple ferroelectric capacitors share a common terminal—offers a compelling route for 3D integration. However, due to the extremely small cell sizes and associated charge signals of the 3D nC-string architecture, sensing circuitry is required to accurately detect the polarization state. In the 2TnC configuration, a dedicated transistor is placed near the common terminal to enable local charge sensing. Alternatively, cells can be read in a FeFET-like mode by detecting the drain current modulation.

At imec a novel test vehicle is currently under development to experimentally explore the 2TnC ferroelectric memory architecture. This platform opens the door to a broad range of research directions, including the comparison between different reading schemes, the investigation of endurance and retention mechanisms, and the impact of size reduction on wafer-level uniformity and device performances. These studies will be essential for understanding the trade-offs between performance, reliability, and scalability, ultimately contributing to the optimization of the device design and the advancement of 3D ferroelectric memory technology.

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Type of work:  15% literature, 65% measurement, 20% modelling.