Control Circuits for High Density 3D Memories

Little known to the general public is the critical role played by memories in all electronic systems.  Nearly a third of the global semiconductor capital expenditure is devoted to memories and more silicon wafers are used for manufacturing memories than for anything else.  The memory market is extremely competitive and characterized by a high rate of semiconductor technology innovation, rivalling or even exceeding that of logic process technologies used for processor units. Testimony to this is the transition of NAND Flash from 2D to 3D manufacturing technology around 2015, which constituted one of the largest paradigm shifts in integrated circuits since their inception in the late 1950’s. Due to the relentless pressure on cost reduction, all memory types are poised to follow this trend to 3D integration and the search for 3D implementations of DRAM and ferroelectric memories is a particularly intense field of research today.

Imec’s memory research programs traditionally have put a lot of emphasis on the development of elementary memory cells, their fabrication process and the required materials and manufacturing tools. However, the memory cell is only half of the solution.  This is illustrated by the invention of the differential sense amplifier circuit by Stein et al. in 1972, which made it practical to produce modern 1T1C DRAM memory. Thus, memory cells can only work in close conjunction with highly specialized control circuits and each new generation of memory technology poses new challenges to these circuits.  This holds true even more so when 3D memory technologies are introduced and the viability of alternative 3D memory cell concepts will hinge on the availability of suitable control circuits.  For this reason, imec seeks to extend the scope of its memory research program to the study of 3D memory control circuits.

Of particular importance and interest to our research program, is the read operation in 3D NAND Flash memories.  A deep understanding is needed of the circuit techniques employed currently by the industry to understand the challenges posed by future technology generations and to evaluate the potential of alternative technology and circuit solutions. A thorough study of the case of 3D-NAND Flash will subsequently benefit the study of the read operation in 3D integrated DRAM and ferroelectric memories.