Design enablement, characterization & technology/system architecture tuning for CMOS2.0

Future integrated circuit (IC) cross-sections are expected to incorporate multiple layers of complementary metal-oxide-semiconductor (CMOS) technologies, each optimized for specific functionalities at a fine granularity. These include the separation of combinational and sequential logic, differentiation between high and low drive strengths, deployment of computation-specific logic gates, active interconnects, and stacked memory layers offering distinct trade-offs between capacity and access latency. This architectural evolution is commonly referred to as the CMOS 2.0 technology paradigm. To fully harness the potential of CMOS 2.0, a holistic optimization strategy is required across all layers of the compute system stack—from device technology up through the software layer. This methodology, termed Cross-Technology Co-Optimization (XTCO), extends the principles of Device-Technology Co-Optimization (DTCO) and System-Technology Co-Optimization (STCO), both of which are already established in academic and industrial practice. The CMOS 2.0 shift, in combination with XTCO, is anticipated to fundamentally transform system design. Addressing these challenges necessitates a coordinated effort along three key axes: (a) technology-level aspects, including synthesis, layout, and sign-off with power and thermal considerations in multi-layered ICs; (b) system-level architectural tuning across cores, interconnects, memory hierarchies, and full system-on-chip (SoC) integration; and (c) software-level optimization. A team of PhD researchers will investigate these domains in a tightly interconnected manner.