Exploration of scale-up and scale-out VPUs in open-source SoCs

Future open-source SoCs targeting advanced nodes will need to utilize the performance benefits offered by the CMOS2.0. The trade-offs between scaling of the units (scale-up) and scaling of the system (scale-out) largely involve the costs of interconnects on multiple levels and the costs of implementing logic (data-paths) in one or two layers of CMOS2.0. This project will focus on the SoC architecture and full-stack software mapping and explore the options to optimize the costs vs. benefits for advanced CMOS2.0 logic and interconnect implementations of a cluster(s) of CPU (e.g., CVA6S++ [2]) and VPU (e.g., ARA-XL+ [1,g3]) units where starting from 1D (vector) processing the complexity is gradually increased to 2D (matrix), 3D (tensor) operations and beyond, and where costs vs. benefits trade-offs can be addressed in much more incremental, and energy-proportional [4] fashion than in prior-art.

This project is complementary to a full-custom design for a TPU, where the challenge of parameterized design and layer-specialized data-path design is addressed statically. In an envisioned SoC platform containing multiple front-end cores (CPUs) and multiple back-end vector processing units (VPUs), the decision relating to routing and localized processing of data are taken at later phases (initialization, run-time). This may be supported by a form of Just-in-Time (JIT) or dynamic binary translation (DBT) implemented by a HW/SW co-design.