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Research update

Backside power delivery options: a DTCO study

Imec highlights the potential of backside power delivery for high-performance computing and evaluates options for backside connectivity


Some major chip manufacturers recently announced the introduction of a backside power delivery network (BSPDN) in their logic roadmap.

In this article, imec, in collaboration with Arm, presents a design-technology co-optimization (DTCO) of one specific implementation of a BSPDN, where nTSVs and buried power rails are used for backside routing. They show how the potential of this BSPDN scheme can be fully harvested in a high-performance compute context.

In addition, they introduce alternative options for backside connectivity at the standard cell level, observing the largest scaling potential for a direct backside connectivity scheme.