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A novel approach for improving gate-stack reliability

Atomic hydrogen treatment to improve NBTI reliability in low-thermal-budget process flows


Negative bias temperature instability can severely affect the reliability of p-type metal-oxide-semiconductor field-effect transistors. In current CMOS fabrication processes, an anneal step at ~900°C – often referred to as the ‘reliability anneal’ – is typically performed to improve the dielectric quality and alleviate this issue. However, in novel integration schemes such as sequential 3D stacking of multiple device tiers, such high temperature steps might become inapplicable. Imec has developed a novel and even more effective solution that also works at much lower temperatures (100-300°C) by directly exposing SiO2 to atomic hydrogen for efficient defect passivation. In this article, Jacopo Franco, Principal Member of Technical Staff at imec and Jean-François de Marneffe, Principal Member of Technical Staff at imec, highlight the breakthrough results, and discuss potential applications beyond sequential 3D. These results were presented at the recent 2020 IEDM conference.