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Towards a process flow for monolithic CFET transistor architectures

Imec highlights critical process steps and modules for monolithic CFET devices


The development of a process flow capable of demonstrating functionality of a monolithic complementary FET (CFET) transistor architecture is complex due to the need to vertically separate nMOS and pMOS devices within the same footprint.

In this interview, Hans Mertens, Steven Demuynck, and Anne Vandooren – three experts from the imec CFET team – explain how they gradually address this complexity.

They highlight CFET-specific process steps and modules and introduce backside connectivity as a key technology enabler to further reduce the size of standard cells.