Nanosheet Transistor Architectures imec
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Entering the nanosheet transistor era

Reviewing benefits and challenges of nanosheet device architectures for 3nm and beyond: nanosheet, forksheet and CFET 


Several foundries recently announced to move from mainstream FinFET to nanosheet transistor architectures for the high-volume production of their 3nm or 2nm logic chips. 

In this article, Naoto Horiguchi, director CMOS device technology at imec, takes us back to the early days of nanosheet transistor development, and looks forward to newer generations of this promising transistor architecture, including forksheet and CFET.

This nanosheet device family will enable to gradually push logic standard cell heights to 4 tracks and below. As such, it can extend the logic roadmap with additional technology generations, in answer to an increasing computing demand.