Article W2W bonding
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Research update

Wafer-to-wafer hybrid bonding: pushing the boundaries to 400nm interconnect pitch

Innovations in Cu/SiCN bonding technology are driven by memory-on-logic stacking needs


Wafer-to-wafer hybrid bonding is an attractive 3D integration technology for stacking multiple heterogeneous chips with high 3D interconnect density.

To expand the application domain towards, e.g., memory-on-logic stacking, the 3D interconnect pitch must scale far below 1µm – today’s state of the art.

This article highlights recent design and technology innovations that have enabled hybrid Cu & silicon-carbon-nitride (SiCN)-to-Cu & SiCN bonding with interconnect pitches down to an unprecedented 400nm.