3D system integrationSemiconductor technology & processing

Temporary bonding and mold process to enable next-gen fan-out wafer-level packaging

Recent progress in the assembly and packaging of chips has brought new challenges to temporary wafer bonding processes. In this article, Arnita Podpod, senior R&D engineer at imec, and Eric Beyne, imec fellow and program director of imec’s 3D system integration program, introduce new temporary bonding solutions and molding materials that answer the needs of a new flavor of fan-out wafer-level packaging. This new process for 3D die-to-wafer assembly was the recipient of the 2019 3D InCites Process of the Year Award. 

In search for a new generation of temporary bonding technologies 

Temporary wafer bonding processes were initially developed for enabling 3D stacked ICs. With 3D stacked IC technologies, dies can be stacked on top of each other using for example die-to-wafer stacking. Through-Si vias and microbumps are used to interconnect the finished dies. These techniques require the processing and handling of ultra-thin substrates, which has been enabled by the first-generation of temporary wafer bonding solutions. By using these technologies, the thinned device wafers on a carrier can now be processed through succeeding multiple backside process steps. At the end of these processes, wafer de-bonding solutions allow the carrier to be separated from the device substrates with only a minimum of stress. 

However, recent advancements in assembly and packaging have brought along new challenges for temporary bonding. An example is the rise of fan-out wafer-level packaging (FO-WLP), a flavour of wafer-level packaging technology that answers the demand for more functionality, increased I/O count, smaller form factor and cost reduction. With fan-out wafer-level packaging, a redistribution layer (RDL) is created that is used to re-route the die connections (I/Os) to the desired (bump) location on top of the die surface. The redistribution layer is created either prior to or after a wafer over-molding step. The function of the epoxy molds is to protect the individual components and hold them all together. 

The processing of these reconstructed over-molded substrates is putting new constraints to temporary bonding. One of the main challenges is stress holding, related to the large mechanical property mismatch between the over-molded substrate and the carrier. Temporary adhesive solutions must now cope with high and varying stress levels throughout the various process steps, while trying to maintain the wafer geometry (i.e., warp and bow). 

Meeting the requirements of a novel FO-WLP technique 

In this article, we introduce advanced molding materials and new temporary bonding and de-bonding solutions. These solutions have been developed to answer the needs of a new flavour of FO-WLP developed at imec: the flip-chip on fan-out wafer-level packaging. More specifically, the challenge was to realize extremely low die shift in combination with low wafer bow and warpage – after wafer over-molding.  

Although specifically developed for this new FO-WLP flavour, the technology may open new horizons for the processing of over-molded substrates. For example, if low-warpage can be achieved, these overmolded substrates can access more standard silicon back-end-of-line process equipment, eliminating the need for dedicated toolsets that can handle large wafer bow.  


Figure 1: Concept of the flip-chip on fan-out wafer-level package. 

Prior to giving more details on the new molding and (de-)bonding technologies, we will briefly summarize the major steps of the flip-chip on FO-WLP technology – as these have set the requirements for the new technology. 

Flip-chip on FO-WLP: a quick summary 

Imec’s flip-chip FO-WLP technology has been developed to push the boundaries of conventional FO-WLP solutions in terms of chip-to-chip connection density. With this FO-WLP approach on 300mm wafers, ultrahigh interconnect density with 20µm pitch have come within reach. The technology is particularly attractive for mobile applications as it enables a cost-effective wide I/O memory-to-logic interconnect in a very small form factor. But it may also become an enabling technology for heterogeneous integration targeting high-performance applications. 

Flip-chip on FO-WLP basically uses a mold-first approach: dies are first assembled on a temporary carrier, followed by wafer over-molding. In a final stage, the redistribution layer is created and connections are made. But contrary to standard mold-first approaches, dies are now over-molded after the formation of the chip-to-chip interconnections. This way, chips are already interconnected before being shifted during the over-molding process. 

The imec team has earlier demonstrated the feasibility of this approach by using a test vehicle that is composed of seven individual (dummy) chip components: wide I/O DRAM, Flash memory, logic, two through-package vias and two Si bridges. The interconnecting Si bridges and the through-package via chips are key components to realize the high-density connections. Through-package via chips are Si dies with through-Si vias (TSVs) and bumps of 40µm pitch. The Si bridges have bumps of 40µm and 20µm pitch. These components form a bridge between the functional dies (e.g. the logic and memory dies), enabling ultrahigh chip-to-chip interconnect densities with 20µm bump pitch. 

Process Flow

Figure 2: Flip-chip on FO-WLP: assembly process flow. 

In a first step of the flip-chip on FO-WLP assembly process flow, the through-package via and logic dies are placed on a carrier wafer with a temporary bonding layer on top. Next, the Si bridge (with 40µm and 20µm bump pitches) is attached using a thermocompression bonding (TCB) step. In this process step, bumps with 40µm pitch are attached to the through-package via side and to the left side of the logic die. The 20µm pitch bumps are attached to the right side of the logic die. In a next step, the wafer is over-molded by a liquid mold compound. Afterwards, the Cu pillars are exposed through grinding – to connect with the redistribution layer later on. After flipping the thinned wafer to a second carrier and removal of the first carrier, the memory dies are assembled using flip-chip technology. A second wafer-level molding and removal of the second carrier complete the process flow. The result is a complete package of only 300-400µm thickness (excluding the solder balls). 

Finding the right adhesive and mold materials 

Throughout the assembly flow, two temporary carrier substrates are being used. Their role in the assembly process puts very specific requirements on the adhesive material that is used for temporary bonding, and on the release material used for de-bonding.  

The main role of the first carrier system is to assemble chips (i.e., the through-package via and logic dies) with extremely high inter-die alignment precision: +/- 3µm die-to-carrier placement accuracy is needed to allow for 20µm bump pitches. Such an accurate placement can be obtained by incorporating alignment marks into the carrier and die designs. The first adhesive material must therefore be sufficiently transparent to enable pattern recognition for alignment. Next, the imec team was looking for a material that allows the dies to be placed at room temperature. At this temperature, thermal expansion issues can be eliminated, enabling more precise die-to-carrier alignment. At the same time, the adhesive must be able to withstand higher temperatures during a subsequent thermocompression bonding (TCB) die-to-wafer bonding step (see steps 5 and 6 in figure 2). And the material must be capable of maintaining the dies in place during the wafer over-molding step. In the end, the adhesive material should also allow carrier-one debonding while maintaining minimum wafer bow.  

The main role of the second carrier is to enable the removal of the first carrier system. When this is removed, the front-side of the original devices can be re-accessed for testing and further processing. A major requirement for this second carrier system is therefore to enable the selective removal of the first carrier, without damaging the reconstructed wafer or increasing warpage. 

Die shift, wafer warpage and bow can also be influenced by the mold material and wafer over-molding techniques. The assembly flow for the flip-chip on FO-WLP involves two separate mold steps. A first over-molding step takes place after the silicon bridge is placed; a second after the memory die is flip-chip attached. It will be key to identify the right combination of temporary bonding and mold materials and processes to guarantee a low wafer distortion and die shift after molding.  

The outcome: record low die shift and wafer warpage 

The team has set up several experiments allowing to evaluate different carrier systems, temporary adhesives and mold materials. In partnership with Brewer Science Inc., a new temporary bonding material for room temperature die bonding has been introduced, referred to as BrewerBOND® C1301. Both liquid and granular forms of advanced mold materials (referred to as M1 and M2) have been explored. The impact of these materials and processes on die placement, die shift and wafer geometry was investigated. 

On blanket wafers, the granule mold material in combination with the temporary bonding material shows more stability than the liquid one when exposed to different temperatures. This can be explained by the higher glass transition temperature of granular vs. liquid mold materials. 

On molded wafers with exposed embedded dies, the combination of a silicon carrier with the new temporary adhesive and advanced mold materials results in less than 2µm die-to-carrier mismatch, even after exposure to temperatures of 200°C for 2 hours – for both granular and liquid molds. An extremely low warpage of less than 200µm was achieved on the full 300mm wafer. These values are way below the ones reported in literature. 

warpage evolution

Figure 3: Warpage evolution at different process steps with liquid (green) and granule (blue) type of molds. Warpage remained low during succeeding process steps.  


Figure 4: Die-to-carrier overlay, post-mold and post-bake, with the liquid mold material. The results show that post-die shift did not change after subjecting the molded wafer to 200°C for two hours – supported by the circle-in-circle images of a die from center, middle and edge of the wafer. A similar result is obtained for the granular mold material. 

The team also explored ways to efficiently de-bond the two carrier systems and remove the adhesive material. For the removal of carrier one, a mechanical de-bonding technique was used that did not affect the second bonding. The use of a mechanical-de-bondable silicon substrate was preferred, as it was compatible with the initial requirement of having alignment marks on the carrier substrate. For carrier two, a laser-assisted de-bonding was chosen for throughput and productivity reasons. Successful selective carrier de-bond has been demonstrated. 


Figure 5: Photograph of a thinned molded reconstructed wafer after carrier 2 laser de-bonding. 


Warpage and die shift are two main challenges when processing molded substrates. The results presented in this study show that the combination of a new temporary bonding material with two different mold material types on a silicon substrate can address these challenges. A quasi-zero post-mold die shift and less than 200µm warpage could be demonstrated.  

The new temporary carrier technology is a key enabler for imec’s flip-chip on FO-WLP. But the importance of the results goes beyond that. First, the achievement of such a very low warpage enables the processing of over-molded substrates in standard silicon equipment. Second, the results open a different avenue for the FO-WLP processing approach in general. For example, fine-pitch redistribution layers in combination with chip-first approaches will now become possible. 

This article originally appeared in the 3D InCites 2020 Yearbook, published March 2020.

About Arnita Podpod 

Arnita Podpod graduated with a master degree in Materials Science and Engineering, and with a bachelor degree in Applied Physics from University of the Philippines. After graduation, she started at NXP Semiconductors as a Project (Materials) and Process Engineer, and progressed to being a Senior Package Development Engineer with Fairchild Semiconductor Phils. Arnita joined imec in 2013 as a Senior R&D Engineer and is currently responsible for both Flip Chip on FO-WLP projects and Pre-Assembly module integration within the imec 3D program. 

About Eric Beyne

Eric Beyne obtained a degree in electrical engineering in 1983 and the Ph.D. in Applied Sciences in 1990, both from the Katholieke Universiteit Leuven, Belgium. Since 1986 he has been with imec in Leuven, Belgium where he has worked on advanced packaging and interconnect technologies. Currently, he is imec fellow and program director of imec’s 3D System Integration program. He received the European Semi Award 2016 for contributions to the development of 3D technologies. 

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