Naoto Horiguchi is a director of the logic CMOS scaling program in imec, in Leuven, Belgium. He started his carrier in semiconductor device R&D at Fujitsu Laboratories Ltd. in 1992. From 1992 to 1999, he was engaged in device development using semiconductor nanostructures in Fujitsu Laboratories Ltd. and the University of California, Santa Barbara. From 2000 to 2006, he was involved in 90-45nm CMOS technology development in Fujitsu Ltd. as a lead integration engineer. Since 2006, he has been with imec, where he is engaged in advanced CMOS device R&D together with worldwide industrial partners, universities, and research institutes. His current focus is CMOS device scaling down to 1nm technology node and beyond.
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25 August 2021